1). Field of the Invention
The present invention relates generally to a semiconductor processing system and, more particularly, to a semiconductor processing system which compensates for depletion of processing gases over a wafer being processed.
2). Discussion of Related Art
Semiconductor devices are manufactured by exposing a silicon wafer to respective processing steps such as the deposition of a layer on the wafer or etching of a layer on the wafer. The wafer is inserted into a semiconductor processing chamber and heated to a temperature sufficient for purposes of processing. Gases are then introduced into the chamber which react with one another or with the wafer to process the wafer. One of the amorphous or polysilicon processing steps carried out on the wafer is the formation of an epitaxial silicon layer on the wafer. Certain benefits, such as proper sealing of the wafer, can be achieved by depositing the amorphous or polysilicon layer on opposing faces of the wafer.
The wafer is supported by means of small seats contacting a lower face of the wafer. By so supporting the wafer the lower face of the wafer can be exposed to the processing gases.
It may in certain instances be required to locate a heat plate below the wafer. A heat lamp may be located to radiate onto the heat plate so that the heat plate is heated. The heat plate, in turn, is used to heat the lower face of the wafer. The processing gases may then flow into a space between the heat plate and the wafer for purposes of processing the lower face of the wafer.
One problem associated with such a wafer-and-heat plate configuration is that the dimensions of the space is such that insufficient processing gases flow through the space between the wafer and the heat plate. The processing gases tend to deplete near an edge of the wafer leaving a central portion of the wafer insufficiently processed. Stated differently, depletion of the processing gas results in more processing tending to occur on the lower face of the wafer near an edge of the wafer than in the central portion of the wafer.